# Arithmetic Built-In Self-Test for Embedded Systems by Janusz Rajski

By Janusz Rajski

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Additional resources for Arithmetic Built-In Self-Test for Embedded Systems

Example text

Yet another version of the count-based compaction is transition counting [76], in which the number of 0 —> 1 and 1 —> 0 transitions that occur at the CUT output is counted. , to detect the actual transition. A slightly different compaction scenario, known as the edge counting, assumes that only positive (from 0 to 1) or negative (from 1 to 0) transitions are counted. 4. Compaction of Test Responses 35 An important class of test-response compaction schemes originates from the work [75], where the concept of checksums for testing purposes was introduced.

22a. Registers T and S are used to store initial values of the corresponding counters. They are in­ corporated into the scan chain, and loaded prior to a BIST session. As the register T is used only at the beginning of testing, it is further modified to act as a signature analyzer, thus making the controller self-testable. During execu­ tion, several signals are fed into T which compacts them into a signature. This signature, which is subsequently scanned out altogether with other test results, allows the integrity of the controller itself to be determined.

An example of a hybrid CA using rules 90 and 150 at alternating sites is shown in Fig. 9. The work presented in [154] demonstrates the existence of the isomorphism between a one-dimensional linear hybrid CA and an LFSR having the same irreducible characteristic polynomial. Despite the same cycle structure, the sequencing of states may still be different between the CA and the LFSR, with the CA having the better randomness distribution [82]. 3. Generation of Test Vectors 23 a phenomenon typical for the LFSRs.