By Richard C. Dorf

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**Extra info for Computers, Software Engineering, and Digital Devices (The Electrical Engineering Handbook Third Edition)**

**Example text**

7. Transitions are between the 20 and 80% levels. 12 are connected externally. The outputs of several gates can therefore share a common pull-down resistor to form a wired-OR connection. The open emitter outputs also provide flexibility for driving transmission lines, the use of which in most cases is mandatory for interconnecting this high-speed logic. A twisted pair interconnection can be driven using the complementary outputs (A þ B) and (A þ B) as a differential output. Such a line should be terminated in an ECL line receiver (10114).

24 shows the D and J-K flip-flops with their characteristic equations along with the T (or toggle) flip-flop and the S-R flip flop. Since bistable devices are asynchronous, fundamental-mode, sequential logic circuits, only one input is allowed to change at a time. This means that for proper operation for a basic latch, only one of the data inputs S or R for an S-R NOR latch (and the NAND implementation) may be changed at one time. , the data input(s) must be stable for a minimum period before the control input C changes the latch from the transparent mode to the memory mode.

25 33 10 10 20 10 20 a See text for explanation of abbreviations. Source: P. Graham, ‘‘Gates,’’ in Handbook of Modern Electronics and Electrical Engineering, C. , New York: WileyInterscience, 1986, p. 871. With permission. 5-V limit set for all other TTL families. Input leakage currents for 74LSxx are specified at Vi ¼ 10 V, and input voltage levels up to 15 V are allowed. The 74LSxx has the additional feature of the Schottky diode D1 in series with the 100-O output resistor. This allows the output to be pulled up to 10 V without causing a reverse breakdown of T5.