TRON Project 1990: Open-Architecture Computer Systems by Dr. Ken Sakamura (auth.), Ken Sakamura (eds.)

By Dr. Ken Sakamura (auth.), Ken Sakamura (eds.)

I desire to expand my hot greetings to you all on behalf of the TRON organization, in this get together of the 7th overseas TRON venture Symposium. The TRON undertaking used to be proposed by means of Dr. Ken Sakamura of the collage of Tokyo, with the purpose of designing a brand new, comprehen­ sive machine structure that's open to world wide use. Already greater than six years have handed because the undertaking was once installed movement. The TRON organization is now made from over one hundred forty co m­ panies and companies, together with 25 in a foreign country corporations or their associates. A simple objective of TRON venture actions is to supply the area a human-oriented laptop tradition, that might bring about a richer and extra pleasing lifestyles for individuals in the course of the international. it truly is our wish to deliver to fact a brand new order on the planet of pcs, according to layout innovations that examine the desires of people firstly, and to permit humans to benefit from the complete merits of those com­ puters of their everyday life. due to the efforts of organization participants, in contemporary months a couple of TRON-specification 32-bit microprocessors were made on hand. ITRON-specification items are carrying on with to seem, and we're now seeing advertisement implementations of BTRON requirements besides. The CTRON subproject, suggest­ whereas, is selling standardization via validation trying out and a portability scan, and items are being advertised through sev­ eral businesses. this is often really a 12 months within which the TRON undertaking has reached the sensible implementation stage.

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It uses a bit fielel in the CSW (Context Status Word) register called DCT and if the SMRNG field becomes larger than the DCT fielel, a trap occurs with clearing the DCT fielel to its maximum value 111 (in binary). So ifyou set the DCT field to 100 in requesting an exception, it is automaticly detecteel by the hardware. Note that the DCT field is includeel in the task context. Seconelly, exceptions that can happen in a non-nestecl extendcd SVC can not always be detected by the value of SMRNG, but can be detecteel by the change of IMASK to 15.

Then, the latter half of this paper discusses a few topics regarding the performance of an OS which conforms to the ITRON2 specification. 00. This kernel was implemented on the TX1 microprocessor, which is one of the TRON specification processors. It has 103 system calls and code size of 20KB. 2. PERFORMANCE PARAMETERS OF A REAL-TIME OS In this section, we define five parameters of a real-time OS performance. Here, we use the words "penalty", "latency" and "cost" in the following manner. A "penalty" is a time elapsed by the OS or the hardware in processing an event.

Figure 1 shows the definition. Please refer to Figure 2 for the meaning of the bar patterns used in the figures from now on. 27 - - - best case ------ warst case Time Interrupt Task etc. I -: ~ ~ ~ ~ ~ ~ ~ -~ - - -, - - - - - - - - Inter -upr penalty I I I I Interrupt Handler - - -I f---------, I I _________ J Interrupt latenc Handler response tc Interrupt Fig. ~ Task switching latency Fig. 2 INTERRUPT LATENCY The interrupt latency is the time during which an OS disables the services to the external interrupts.

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